There have been several prior works that deal with heterogeneity at various levels of abstraction, ranging from the technology to the architecture-level and techniques to map applications on such platforms. 
The technology-level aspects of heterogeneous integration of CMOS with emerging technologies using 3D technology have been explored in~\cite{ionescu-3D}.
While static and dynamic techniques in architecturally heterogeneous multicore have been examined before in~\cite{morphcore}, thermal-aware application scheduling in~\cite{prometheus} and voltage scaling techniques in 3D architectures in~\cite{hhlee-3D-dvfs}, our work extends such techniques to device heterogeneity as well. 

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% The authors in ~\cite{ionescu-3D} analyze various aspects of heterogeneous device integration in 3D technology. Our work, while based on this concept, extends this further by incorporating thermal and yield models as well as application mapping algorithms on heterogeneous 3D architectures. 
% While static and dynamic techniques in architecturally heterogeneous multicore have been examined before in~\cite{morphcore}, thermal-aware application scheduling in~\cite{prometheus} and voltage scaling techniques in 3D architectures in~\cite{hhlee-3D-dvfs}, our work extends such techniques to device heterogeneity as well.
